1. Field of the Invention
The present invention relates generally to semiconductor memories and in particular to electrically-programmable read-only-memories (EPROMs) and electrically-erasable-programmable read-only-memories (EEPROMs) arrays which avoid the use of field oxide islands to provide electrical isolation.
2. Background Art
An electrically-programmable read-only-memory EPROM and an electrically-erasable-programmable read-only-memory (EEPROM) are non-volatile memories which maintain data stored in the memory when power is removed. EPROM devices are erased by exposure to ultraviolet light. EEPROM devices, also known as a flash memories, add complete electrical erasure and reprogramming functionality to the non-volatility of the EPROM.
FIG. 1 is a diagram of a conventional EPROM or EEPROM memory array 10 of 16 memory cells. FIGS. 2A and 2B are taken through section lines 2A--2A and 2B--2B of FIG. 1. Exemplary memory cell 12A includes a drain region 14 and source region 22.
Adjacent exemplary memory cell 12B includes a drain region 14 shared in common with memory cell 12A.
A word line 16 made of doped polysilicon (poly 2) functions as a control gate for the transistors. Floating gates 24 are made of doped polysilicon (poly 1) and are disposed between the transistor memory cell channels and the word lines 16 (FIG. 2B). A thin oxide 20 extends over the surface of the memory cells and between the floating gates 24 and the memory cell channel region.
Contact openings 15 are formed so that the metal bit line 18 can contact the drains of the memory cells. As can be seen in FIG. 1, buried N+ bit lines 18 function to connect the source regions together. As shown in FIG. 2B, the source regions 22 are comprised of an N+ region.
FIG. 3 illustrates the manner in which the memory cells 12 are programed. A relatively high voltage Vpp (typically 13 volts) is applied to the poly 2 word line 16 (the control gate). An intermediate voltage Vd (typically 6 volts) is applied to the drain region 14 and a low voltage Vss (typically 0 volts) is applied to the source region 22. "Hot" electrons are generated at the edge of the drain. The high voltage Vpp on the control gate electrode (poly 2 word line) 16 causes some of the free electrons to cross the gate oxide 20 and enter the floating gate (poly 1) 24 where the electrons remain trapped.
Erasure is accomplished by discharging the floating gate 24. In the case of an EPROM cell, the discharge is accomplished by exposure to U.V. light. In the case of a flash memory cell, the erasure mechanism is Fowler-Nordheim tunneling, as is well known.
A memory cell is read by applying voltage Vd (typically +3 volts) to the drain and grounding the source (Vss). A positive voltage (Vcc) is applied to the control gate (word line) 16. If the cell had been previously programmed, the electrons will have increased the threshold voltage of the cell and the gate/source voltage will not be sufficient to render the cell conductive. Thus, no current will flow. Conversely, if the cell has not been programmed, the gate/source voltage will be sufficient to render the cell conductive and current will flow. Current flow or lack thereof is detected by a sense amplifier (not depicted).
FIG. 4 is a schematic diagram of a segment of an exemplary conventional memory array which includes a total of twelve memory cells Q1-Q12, with cells Q1-Q4, Q5-Q8 and Q9-Q12 being in separate rows and having common word lines WL-1, WL-2 and WL-3, respectively. The three depicted bit lines are BL-1, BL-2 and BL-3. The appropriate bit lines are connected to four exemplary select transistors 28A-28D, there being at least one select transistor associated with each column of memory cells. Bit lines BL-1 and BL-3 comprise N+ lines which are strapped with metal bit lines (not depicted) which can be accessed by way of contacts 30A and 30B. Bit line BL-2 is a buried line which can be accessed indirectly through select transistors 28B and 28C.
Select transistors 28A and 28B are in a common row and have their control gates connected to select line Select 1. Similarly, select transistors 28C and 28D are in a common row and have their control gates connected to select line Select 2. Preferably, a second set of select transistors 28A', 28B', 28C' and 28D' are provided which are connected to the opposite end of the memory cell segment in the same manner as select transistors 28A, 28B, 28C, and 28D. A second pair of select lines Select 1' and Select 2', driven in parallel with lines Select 1 and Select 2, respectively, are provided for controlling the second set of select transistors. The second set of select transistors are connected to contacts 30A' and 30B' which are driven in parallel with contacts 30A and 30B, respectively.
Referring to FIG. 5, a plan view of a layout of an integrated circuit implementing the memory array segment of FIG. 4 may be seen. The second set of select transistors 28A', 28B', 28C' and 28D' are not depicted. Each cell of the array is located in the region near the intersection of a bit line BL and a word line WL. Select transistor 28A is disposed in the region near the intersection of bit line BL-1 and select line Select 1. Similarly, select transistors 28B, 28C and 28D are located near the regions of the intersection of line Select 1/bit line B1-3, line Select 2/bit line Bl-1, and line Select 2/bit line BL-4, respectively.
Electrical isolation is provided by the use of field oxide (FOX) regions. When the FOX regions are disposed in the array of select transistors or memory cells, they are commonly referred to as FOX islands. By way of example, FOX island 32A extends down into the regions between transistors 28A and 28B. There is also a FOX island 32C between transistor 28C and an select transistor not depicted. As a further example, a FOX island 32D is disposed between transistors 28C and 28D.
The select transistors 28A-28D are typically conventional MOS transistors rather than the floating gate transistor such as devices Q1-Q12 used as memory cells. However, it has become conventional to simplify circuit layout by using the same floating gate transistor devices used as memory cells as the select transistors. The floating gate select transistors are all unprogrammed so that no charge exists on the floating gate. Accordingly, the threshold voltage of the floating gate transistor is sufficiently low to permit the cell to perform the select function accomplished by conventional select transistors.
The use of the same type of floating gate transistor in both the memory cell array and the cell select section has provided an improved memory layout scheme. However, shortcomings remain in such conventional approaches.
The FOX islands 32 located in the FIG. 5 memory are disadvantageous for several reasons. First, the intersection of the FOX islands 32 and bit/select lines represents the largest step in the array. FIG. 6 shows a cross-section taken through section line 6--6 of FIG. 5 along the select line Select 2. The maximum height of the structure is the combination of select line Select 2 and the poly 1 line 24 above the FOX islands 32.
Referring to FIG. 7, which is a cross-section taken from FIG. 5 and which is at right angle to the FIG. 6 cross-section, the distance from the center of the FOX island 32D to the top surface of the island is typically about 2000 .ANG.. The thickness of the poly 1 floating gate 24 is typically 2000 .ANG. and the thickness of the dielectric ONO (oxide-nitride-oxide) sandwich layer 40 is 300 .ANG.. Added to this is the poly 2 layer and the tungsten silicide layer which total 4500 .ANG. and which form the Select 2 line. This gives a grand total of approximately 8800 .ANG.. It is difficult to reliably planarize a deposited oxide layer, such as BPSG (borophosphosilicated glass) over a step of this magnitude.
In addition, the presence of a FOX island 32 disposed in the memory array results in a tendency to produce Poly 1 stringers at Poly 1 and SAE etch (self aligned etch). Further, the FOX islands increase the size of the array and also increase the resistance of the bit lines.
The present invention eliminates the necessity of providing electrical isolation between select transistors using FOX islands. Accordingly, the disadvantages arising from the use of FOX islands noted above are eliminated. These and other advantages of the present invention will become apparent to those skilled in the art upon a reading of the following Detailed Description of the Invention together with the drawings.